This invention relates generally to delay circuits and specifically to a skew generator for measuring a pulse width, incorporating delay elements comprising CMOS (Complementary Metal Oxide Semiconductor) and BICMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated circuit devices. As is well known, similar devices on a common integrated circuit chip exhibit a very high degree of correlation to each other, whereas similar devices on different chips exhibit very poor correlation. For example, it is not uncommon for transistors or other devices on the same IC chip to vary in operating characteristics by less than 1%, whereas similar devices on different chips may vary by 20% or more.
The elements and circuits in the preferred embodiment of the invention utilize BICMOS devices, such as transmission gates and inverters. The current switching ability of these devices is a direct function of applied gate voltage. Within operating limits, the higher the applied gate voltage, the larger the current flow in the device. The invention generally provides a novel and superior delay circuit for integrated circuit use that is especially suitable for high frequency applications where the delays are in the range of a few nanoseconds. The present invention is specifically directed to a pulse width measuring arrangement using novel voltage controlled delay (VCD). The invention claimed in copending application Ser. No. 07/614,188 now U.S. Pat. No. 5,105,108 is directed to a precise phase locked loop (PLL) controlled delay element; that claimed in application Ser. No. 07/613,175 is directed to a frequency multiplier circuit using voltage rolled delay elements; and that claimed in application Ser. No. 07/613,178 is directed to a novel voltage controlled delay element.